1. Field of the Invention
Embodiments of the present invention relate, in general, to electronic equipments comprising at least two cores (i.e. processors or micro-controllers) each capable of executing instructions embodied as software.
2. Relevant Background
As is known by one skilled in the art, a core (also known as a microprocessor, processor core, processor or micro-controller) is a component of an electronic equipment which is provided for running software, i.e. code that is stored on an external ROM (“Read Only Memory”), such as a boot ROM, but not on the core internal ROM. Accordingly the software to be run has to be provided to the core in order to be executed. Several memory configurations may be used either for storing the software or for its execution.
In addition a core needs a dynamic memory, generically called RAM (for “Random Access Memory”), to temporarily store data associated with the running software and/or code for this software. Generally a core comprises an internal RAM, whose storing capacity (or size) is in most cases not sufficient to store all the needed data. In such a case an external RAM has to be associated with the core.
For example, the software to be executed can be stored in a NOR flash memory and executed from this NOR flash memory if allowed by its memory interface. For example a Pseudo-Static RAM (“PSRAM”) can be used in association with a NOR flash memory to provide for dynamic memory storage of data associated with running software. In a variant of this configuration, the NOR flash memory can be replaced with a NAND flash memory, and the PSRAM can be replaced with Synchronous Dynamic RAM (“SDRAM”). In this variant the NAND flash memory content (the code to be executed) must be loaded into the SDRAM prior to running it because a NAND flash interface does not support direct code execution. Other memory configurations may be envisaged depending on the storing capacity needed (PSRAMs are cheaper than SDRAMs in lower densities, but SDRAMs are cheaper than PSRAMs in high densities) or on the Printed Circuit Board (“PCB”) area that might be allocated for the memory components.
Some specific problems appear when applying these memory configurations to multi-core electronic equipments. For the sake of clarity one will consider hereafter the dual-core case.
In a dual-core electronic equipment, two cores (processors or micro-controllers) cooperate to achieve the equipment full potential. Accordingly, both cores have to be provided with software that is initially stored somewhere in external ROM(s) in the electronic equipment. In addition the cores must execute the software in some memory area while needing a RAM area (internal and/or external) for at least dynamic memory storage. Two classes of memory configuration are candidates to support such technical constraints.
In a first class, a first core manages the storage of both portions of software (for instance into a NAND flash memory) and provides the second core with the software portion it has to execute (for instance by copy from the NAND flash memory to a RAM) at each equipment boot. In this case, each core must have its own RAM for data storage (or a more complex shared RAM to serve both cores), but the RAM memory for the second core has also to be designed and designated (in storage capacity (or size) and performance) in order to allow for internal software execution (because the second core cannot execute software from elsewhere). Such a constraint implies that the first core must act as a “master” while the second core acts as a “slave”, at least during each boot phase, which also impacts the security policies (i.e. when software has to be verified prior execution by a core). The drawback of this first class resides in the time required at each boot to transfer software into the second core's RAM. This elapsed time might be not negligible (typically several seconds) and could penalize the overall equipment boot time.
In a second class, each core has its own memory configuration (for instance a first core with a NOR flash memory and a PSRAM, and a second core with a NAND flash memory and a SDRAM). This second class allows the dual processor core to reuse existing and proven single-core configurations on each side (behaving as two independent systems), and avoids issues that could arise from a common memory configuration (for instance an increased boot time). However this second class has two main drawbacks: first it implies higher cost and PCB area as each core has to be able to download its own software from an external source; and second having duplication of memories is more power consuming, which means that the power consumption cannot be optimized from an equipment wide perspective.
These and other deficiencies of the prior art are addressed by one or more embodiments of the present invention, as described by way of example herein.